1. Field
The embodiment relates to a delay adjusting circuit.
2. Description of Related Art
A delay adjusting circuit using a bias signal from a DLL as a reference is disclosed in Japanese Patent Publication No. H11-261408. As shown in FIG. 11 of aforementioned Japanese Patent Publication, a parent circuit 101 and child circuit 102 are provided, the circuit 101 that feed-back controls and generates an inner signal CKin having the same period or phase as that of an inputted reference signal CKr, and the circuit 102 that receives the inner signal CKin and a control signal CS from the parent circuit 101 to generate a timing signal TS having a predetermined timing to the reference signal CKr are configured. According to the conventional delay adjusting circuit, a plurality of timing signals each synchronized with a reference clock and having a predetermined phase can be generated with a simple constitution and at high precision.
Additionally, another related art is disclosed in Japanese Patent Publication No. 2005-012666.